Path: utzoo!mnetor!uunet!husc6!bbn!rochester!cornell!uw-beaver!tikal!ole!upton
From: upton@ole.UUCP (Mike Upton)
Newsgroups: comp.arch
Subject: Re: Cray-3 ?
Message-ID: <417@ole.UUCP>
Date: 22 Mar 88 18:36:27 GMT
References: <242@litp.UUCP>
Reply-To: upton@ole.UUCP (Mike Upton)
Organization: Seattle Silicon Corporation, Bellevue, WA.
Lines: 52



The folowing data was presented at the 1987 IEEE GaAs Symposium.
The paper was entitled:
	CRAY-3: A GaAs Implemented Supercomputer System.
	Dave Kiefer-CRAY
	John Heightley-Gigabit Logic

For anyone who doesn't know, Gigabit is a Gallium Arsenide foundry
with a line of SSI and MSI GaAs parts, they are doing the fab work for
CRAY for the CRAY 3.

This is Table 1 as persented in the paper:

ATTRIBUTE	CRAY3		CRAY2

GFLOPS		>10		1.2

Clock		500MHz		244MHz

Power		150kW		150kW

Size		32" octagon	53" diameter
		34" high	45" high

Technology
		GaAs DFET	Si ECL
		200 gates/chip  16 gates/chip
		
prop delay
		80ps internal	350ps internal
		200ps external	650ps external

packageing	Direct Die to	Packaged devices
		board			


other numbers cited in the paper include

memory:	1 Gbyte   "local memory only requires 6ns access time ..."
	40K chips

Logic:  50K chips, ~200 different designs.

the paper goes into some depth about the yield of the GaAs process.
It didnt say in the paper, but I believe the 3 will contain 16
processors.

CRAY is a registered trademark of Cray Research, Inc.
-- 
Michael Upton@Seattle Silicon (uucp: ...uw-beaver!tikal!ole!upton)
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