Path: utzoo!dciem!nrcaer!xios!greg
From: greg@xios.XIOS.UUCP (Greg Franks)
Newsgroups: comp.arch
Subject: Today's dumb question...
Message-ID: <503@xios.XIOS.UUCP>
Date: 24 Mar 88 20:27:05 GMT
Article-I.D.: xios.503
Posted: Thu Mar 24 15:27:05 1988
Reply-To: greg@xios.UUCP (Greg Franks)
Organization: XIOS Systems Corporation, Ottawa, Ontario, Canada
Lines: 17


I really hate to break up this interesting discussion on MIPS and VIPS
et al, but a question has come to mind....

RISC generally implies single instruction per clock cycle, and a
load/store type architecture.  Now for _tightly coupled_
multiprocessing, one needs some sort of atomic test-and-set instruction. 
How do the various RISC chips provide this function, with LOCK prefixes,
or with some other technique?

Sign me
   Just curious...
-- 
Greg Franks                   XIOS Systems Corporation, 1600 Carling Avenue,
utzoo!dciem!nrcaer!xios!greg  Ottawa, Ontario, Canada, K1Z 8R8. (613) 725-5411.
       "Those who stand in the middle of the road get
               hit by trucks coming from both directions." Evelyn C. Leeper.