Path: utzoo!mnetor!uunet!steinmetz!ge-dab!codas!pdn!ard
From: ard@pdn.UUCP (Akash Deshpande)
Newsgroups: comp.arch
Subject: Re: Today's dumb question...
Message-ID: <2676@pdn.UUCP>
Date: 30 Mar 88 14:55:21 GMT
References: <503@xios.XIOS.UUCP>
Organization: Paradyne Corporation, Largo, Florida
Lines: 23

In article <503@xios.XIOS.UUCP>, greg@xios.XIOS.UUCP (Greg Franks) writes:
>                                Now for _tightly coupled_
> multiprocessing, one needs some sort of atomic test-and-set instruction. 
> How do the various RISC chips provide this function, with LOCK prefixes,
> or with some other technique?
> Greg Franks

	RISC people (as I discovered at ASPLOS II, San Jose, Oct 87) would
	rather not speak of parallel processing. Reminds me of the ostrich.
	Ask them - "how are you going to maintain cache coherency, TLB
	flushing, accesses integrity, etc in a parallel processing system?"
	and they will say "why do you want parallel processing when one
	RISC machine is so much faster than even parallel CISCs?"

	I would prefer a philosophy that allows for clean parallelisability
	over any single cpu speedups.

							Akash
-- 
Akash Deshpande					Paradyne Corporation
{gatech,rutgers,attmail}!codas!pdn!ard		Mail stop LF-207
(813) 530-8307 o	 			Largo, Florida 34649-2826
Like certain orifices, every one has opinions. I haven't seen my employer's!