Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!oliveb!sun!joe!petolino
From: petolino%joe@Sun.COM (Joe Petolino)
Newsgroups: comp.arch
Subject: Re: Today's dumb question...
Message-ID: <47638@sun.uucp>
Date: 31 Mar 88 00:20:16 GMT
References: <503@xios.XIOS.UUCP>
Sender: news@sun.uucp
Reply-To: petolino@sun.UUCP (Joe Petolino)
Organization: Sun Microsystems, Mountain View
Lines: 12

>RISC generally implies single instruction per clock cycle, and a
>load/store type architecture.  Now for _tightly coupled_
>multiprocessing, one needs some sort of atomic test-and-set instruction. 
>How do the various RISC chips provide this function, with LOCK prefixes,
>or with some other technique?

SPARC provides this function with an atomic test-and-set instruction.  From a
processor chip's point of view, 'store-but-look-at-the-old-contents' is not
much different from a simple 'store', so RISC does not necessarily preclude a
test-and-set instruction.  The really difficult part of interprocessor
synchronization comes at the system level, outside of the processor chip.

-Joe