Path: utzoo!mnetor!uunet!husc6!bloom-beacon!tut.cis.ohio-state.edu!mailrus!ames!oliveb!sun!gaas!garner
From: garner@gaas.Sun.COM (Robert Garner)
Newsgroups: comp.arch
Subject: Re: Today's dumb question...
Message-ID: <47649@sun.uucp>
Date: 31 Mar 88 00:57:31 GMT
References: <503@xios.XIOS.UUCP>
Sender: news@sun.uucp
Reply-To: garner@sun.UUCP (Robert Garner)
Organization: Sun Microsystems, Mountain View
Lines: 44
Keywords: SPARC, test_and_set, Am29000, floating-point


> Now for _tightly coupled_multiprocessing, one needs some sort of 
> atomic test-and-set instruction.  How do the various RISC chips
> provide this function, with LOCK prefixes, or with some other technique?

The SPARC instruction set includes two instructions for this purpose:

        LDSTUB  -  Load/Store Unsigned Byte  -  reads a byte from memory
                  and then rewrites the same byte to -1. 
	SWAP  -  exchanges an integer register and a memory word.

LDSTUB and SWAP are currently implemented as multi-cycle operations.
Between the load and the store, the processor asserts a signal to
the memory (or I/O) bus that prevents intervening accesses.
(A precise requirement is that, if these instructions are
issued by more than one processor, they must execute in some serial order.)

Assuming a specialized memory system that includes an arithmetic unit,
SWAP can also implement the Fetch_and_Add instruction.


On another subject, I recall some confusion in an old msg about SPARC's
multiply-step instruction (MULScc).  The author thought that
MULScc was limited to signed multiplies.  This is certainly not
true:  MULScc implements both signed and unsigned 32x32 multiplies.

[BTW, I noticed that the Am29000 has three instructions--Multiply Step
(MUL), Multiply Last Step (MULL), and Multiply Step Unsigned (MULU).
MULU and MULL seem unnecessary since the fix up for
32x32 unsigned multiplies (or a negative multiplier
in the case of signed multiplies) requires only 3 cycles.] 


On yet another subject, am I still correct in believing that AMD's
Am29C327 floating-point coprocessor does NOT directly execute
the Am29000 floating-point instruction set?  In other words,
must Am29000 instructions such as FMUL and FEQ be emulated
via a trap handler?  Wouldn't this make them too slow?
-----------------------------------
          Robert Garner

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