Newsgroups: comp.sys.cbm
Path: utzoo!utgpu!jarvis.csri.toronto.edu!godzilla.ele.toronto.edu!leblanc
From: leblanc@godzilla.ele.toronto.edu (Marcel LeBlanc)
Subject: Re: 1541 coding question
Message-ID: <8803160632.AA02595@godzilla.ele.toronto.edu>
Summary: 1541 encoding
Keywords: 1541 rom
Organization: EECG, University of Toronto
References: <24611@amdahl.uts.amdahl.com> <8301@tut.cis.ohio-state.edu>
Date: Wed, 16 Mar 88 01:32:45 EST

In article <8301@tut.cis.ohio-state.edu> erd@tut.cis.ohio-state.edu (Ethan R. Dicks) writes:
>In article <24611@amdahl.uts.amdahl.com> dwl10@amdahl.uts.amdahl.com (Dave Lowrey) writes:
>>I have a question regarding 1541 programming. I have been studying the ROM
   ... 
>>c100  CLV
>>c101  BVC  $c101
   ...
>>My question is: exactly why/when is the oveflow flag set, and who is
>>setting it?
   ...
>
>Specifically, the overflow flag is set by _hardware_, not software. There is
>a pin (I can't remember which one) which sets the overflow flag.  In the
>1541, this pin is tied to the output of a Nand, which checks the byte stream
>from the heads.  If the pattern is $FF, then the line gets pulled.  The SYNC
				 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^       ^^^^
>  ...
>-ethan
>
	The OVERFLOW bit is indeed set by hardware, but not as a result
of a SYNC character being detected.  The Overflow bit is set when a byte
is ready to be read (from $1C01).  When eight bits have been read from the
disk surface, the processor is signalled by setting the .V bit.  A SYNC
character is detected by polling bit 7 of $1C00:

	waitsync	bit $1C00
			bpl waitsync
			...

>>                          Dave Lowrey
>
>-- 
>Ethan R. Dicks      | ######  This signifies that the poster is a member in
>Specialized Software|   ##    good sitting of Inertia House: Bodies at rest.


  Marcel A. LeBlanc
  University of Toronto -- Toronto, Canada
  also: LMS Technologies Ltd, Fredericton, NB, Canada

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-- 

  Marcel A. LeBlanc
  University of Toronto -- Toronto, Canada
  also: LMS Technologies Ltd, Fredericton, NB, Canada