Path: utzoo!utgpu!water!watmath!clyde!att-cb!att-ih!pacbell!ames!lll-lcc!pyramid!prls!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: MIPS R3000??? Message-ID: <1969@winchester.mips.COM> Date: 3 Apr 88 01:27:22 GMT References: Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 74 In article zs01+@andrew.cmu.edu (Zalman Stern) writes: >I saw an announcement for the MIPS R3000 processor on the Dow Jones News... as did Randall Jesup earlier, and a bunch of people sending me mail, so: R3000 CPU & R3010 FPU chips: 1) Instruction set. Same as R2000/R2010. In R2000 mode & package, acts like R2000. In R3000-mode (172-pin package), the CPU can do reset-time-selected multi-word refill on cache-miss, plus some other memory-system-interface enhancements, such as better handling of partial-word stores, etc. It also can address up to 256KB each of I&D cache. The R3010 is basically a shrunken R2010. 2) Technology The R2000 is 2.0micron (drawn); the R3000 is 1.2micron (drawn), .8micron (effective channel length). People often refer to an "X-micron technology" without specifying which measure, showing that the VLSI folks have the problem equivalent to vax-mips, ibm-mips, peak-mips, etc. :-) An entire CPU core module (CPU, FPU, 4 write buffers, 128KB of cache, memory interface control, etc) fits easily on a 6"x7" board. 3) Performance - overall 20-vax-mips @ 25MHz with a good memory system (see below). Assume usual caveats about mips/VUP, etc being a range, not a point, i.e., expect 14-28 VUP, versus VAX 11/780 with good compilers. The performance improvements come from: a) Clock speed-up b) More efficient cache<->main memory interface Item a) helps everything. Item b) helps large programs (like Spice, kernel- intensive runs, etc) a lot, but does relatively little for small ones that already had very high cache-hit ratios. Real programs improved more than toys (for example, Spice looks about 2.5-2.7X faster than M/1000). 4) Performance - the most familiar numbers Machine Chip Clock mips Cycles/ KDhrys MWhets Mwhets LNPK DP LNPK SP MHz (VUP) VUP 1.1 -O3 DP SP FORTRAN FORTRAN MFlops MFlops M/1000 R2000 15 10 1.5 24 8 10 1.5 3.6 M/???? R3000 25 20 1.25 42 14 18 4.0 7.0 The R3000 numbers above are simulations for SYSTEM performance, using the parameters below for M/????. (We do have working chips here running UNIX fine at speed; we just don't yet have the final memory boards.) System parameters: cache size: 64K I-cache + 64K D-cache read latency: 12 cycles refill: 16 words, 1 word/cycle, for both I&D caches write buffer: 4-deep writes: 2 cycles/write within same page (I don't recall the time for random writes). That's probably all I can say on that until the systems product that contains this design is announced. The numbers assume the MIPS 1.30 compilers, which do a better job of FP-scheduling than the older ones. 5) More information. A bunch of people have been asking me for detailed architecture info: there is now a book (which covers it at the programming level, where R2000 == R3000): MIPS R2000 RISC Architecture, by Gerry Kane published by Prentice-Hall, Inc. Englewood Cliffs, NJ. 07632 ISBN 0-13-584749-4 I don't think it's stocked in bookstores yet, but it should be orderable. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086