Path: utzoo!mnetor!uunet!lll-winken!lll-tis!mordor!sri-spam!sri-unix!garth!walter
From: walter@garth.UUCP (Walter Bays)
Newsgroups: comp.arch
Subject: Re: Today's dumb question...
Message-ID: <588@garth.UUCP>
Date: 31 Mar 88 19:06:49 GMT
References: <503@xios.XIOS.UUCP> <2676@pdn.UUCP>
Reply-To: walter@garth.UUCP (Walter Bays)
Organization: INTERGRAPH (APD) -- Palo Alto, CA
Lines: 22

In article <2676@pdn.UUCP> ard@pdn.UUCP (Akash Deshpande) writes:
>	RISC people (as I discovered at ASPLOS II, San Jose, Oct 87) would
>	rather not speak of parallel processing. Reminds me of the ostrich.
>	Ask them - "how are you going to maintain cache coherency, TLB
>	flushing, accesses integrity, etc in a parallel processing system?"
>	and they will say "why do you want parallel processing when one
>	RISC machine is so much faster than even parallel CISCs?"

Most RISC computers are, in a limited sense, multiprocessors, because
you'll want at least an 80286 or something for an IOP.  The Clipper has
bus-watch hardware in the CAMMU's (Cache and Memory Management Unit) to
assure cache and TLB consistency in copy-back mode.  And yes, there is
a test-and-set instruction.  Of course you couldn't put too many
Clippers (or any fast CPU) on a bus before it saturated...  I'd rather
not talk about it :-)
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