Path: utzoo!mnetor!uunet!yale!mfci!root
From: root@mfci.UUCP (SuperUser)
Newsgroups: comp.arch
Subject: Re: Motorola 88000 and others
Message-ID: <323@m3.mfci.UUCP>
Date: 6 Apr 88 01:11:27 GMT
References: <1168@csun.UUCP>
Reply-To: mfci!colwell@uunet.UUCP (Robert Colwell)
Organization: Multiflow Computer Inc., Branford Ct. 06405
Lines: 44
Keywords: mc88000 RISC parallel-units

In article <1168@csun.UUCP] sef@csun.UUCP (Sean Fagan) writes:
]I was reading in some trade rag (sorry, forget which) about the MC88000,
]which uses a 'scoreboard' to have up to 3 instructions executing
]simultaneously (plus whatever pipelining the thing has).  Also, someone
]mentioned here a few weeks ago that his company's chip was capable of doing
]a floating-point divide (or multiply, I forget that and which company; may
]have been MIPS) along with some other instruction, also simultaneously.
]The thing I find funny is that these people seem to think that these things
]are wonderful new ideas, yet I routinely work on a CDC 170 type machine,
]which can do a divide, a multiply, a floating point add or subtract, an
]integer add or subtract, and an address calculation, all at the same time.
]Not only that, but all but the divide are pipelined so that it can start
]a new operation each clock cycle (except the multiply, which needs to do it
]every other cycle).  (The Cray can do more, as can the Cyber 205 and ETA 10.)
]Now, after the comment, a question:  does anybody know what non-mainframes
]and non-supers have parallel functional units (preferably pipelined)?
]How abuot how popular these machines are, what their speeds are, etc?
]
]
]-- 
]Sean Fagan                   uucp:   {ihnp4,hplabs,psivax}!csun!sef
]CSUN Computer Center         BITNET: 1GTLSEF@CALSTATE
]Northridge, CA 91330         (818) 885-2790
]"I just build fast machines."  -- S. Cray

Just having multiple functional units is interesting but insufficient.
You also require the means to control these functional units, and you
need a way to give them enough things to do that your application 
achieves the performance you require.  Vector machines like those you
mention above do indeed have parallelism built into their architecture,
but the way they invoke it at run time is to execute vector instructions,
which can only do repetitive operations on aggregate data sets.  The
main task of their compilers is to find low-level parallelism that they
can somehow coerce into the operators provided in the hardware.  If your
application does not need the operator built in, but rather some other
one, you're pretty much out of luck.

The machine we make tackles this problem directly, but rather than bore
other readers I'd refer you to our ASPLOS-II paper for starters.

Bob Colwell            mfci!colwell@uunet.uucp
Multiflow Computer
175 N. Main St.
Branford, CT 06405     203-488-6090