Path: utzoo!mnetor!uunet!littlei!omepd!radix!jimv
From: jimv@radix (Jim Valerio)
Newsgroups: comp.arch
Subject: Re: Press Release: Intel announces 80960 architecture
Message-ID: <40@radix>
Date: 10 Apr 88 10:46:40 GMT
References: <3358@omepd> <10320@steinmetz.ge.com>
Reply-To: jimv@radix.UUCP (Jim Valerio)
Organization: Radix MicroSystems, Beaverton
Lines: 39
Keywords: 80960, RISC, embedded control

In article <10320@steinmetz.ge.com> davidsen@crdos1.UUCP (bill davidsen) asks:
>  2) why didn't they release [the 80960] instead of the 80386?

Instead?  The 386 was a guaranteed business success; it would have been
crazy not to capitalize on the marketplace.

Perhaps a better question is why weren't both architectures sold back then?
As I understand it, there were lots of reasons, including but certainly not
limited to concern about whether there was sufficient Fab capacity for both
processors, and what message two "competing" processor architectures would
give to customers.

You should also remember that around the time this was happening, Intel was
reporting losses for the first time since it had started being profitable
(1972?), and tight times aren't usually the best times for unnecessary risks.

>  4) what about memory management?

Also announced was the 80960MC.  "The 80960MC is a military qualified version
of the KB with memory management and Ada tasking support."

>  3) why is it for "embedded applications" (as opposed to general use)?

The simple answer is that that is the organization that wanted a new processor
architecture was the embedded controller organization, and not the
microprocessor organization, which seems to be firmly committed to future
86 family products.

Personally, I see a marketing tightrope being walked here.  You will note that
the memory management version is only being announced with military spec's,
presumably also at military prices.  I expect that Motorola is walking a
similar line with the 68K and 88K product lines.

>  1) why now?

Sorry, I won't touch this.  :-)

--
Jim Valerio	{verdix,omepd}!radix!jimv, "radix!jimv"@omepd.intel.com