Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!ll-xn!mit-eddie!uw-beaver!microsoft!kenr
From: kenr@microsoft.UUCP (Kenneth Reneris)
Newsgroups: comp.arch
Subject: Re: Press Release: Intel announces 80960 architecture
Message-ID: <1381@microsoft.UUCP>
Date: 12 Apr 88 03:02:05 GMT
References: <3358@omepd>
Organization: Microsoft Corp., Redmond, WA
Lines: 30
Keywords: 80960, RISC, embedded control

A recent Intel press article forwarded by Steve McGeady states:
(intelca!omepd!mcg)

> INTEL ANNOUNCES FIRST EMBEDDED CONTROL PRODUCTS AND TOOLS BASED ON NEW
>                       80960 ARCHITECTURE
  ...
> "The 80960 embedded processors provide significant price-performance
> advantages over most other single-chip, 32-bit embedded solutions," said
> Alan Steinberg, product line marketing manager. "For example, the 80960KB
> is the only processor available which integrates an on-chip floating-point
	 ^^^^
> unit - at four MegaWhetstones - with a 20MHz clock. That is more than
> twice The performance at one-half the cost of other available
> processors."
  ...

Inmos Corp's transputer T800-20 is also a single chip CPU with an integrated
FPU. As a 20Mhz RISC processor it also runs 4 million whetstones a second.
(Reference material: Electronic, Nev 27, 196. p. 57. & Electronics, Aug 20,
1987). I'm not sure what "4.5 VAX MIPS" is, but a single T800-20 breaks the
stop watch at 15 MIPS. In addition, the multitasking is all handled by the
hardware, in the microcode (along with message passing). It has four link
lines with operate at 20Mbit/sec in each direction. Last I knew Inmos was
working on releasing a 30Mhz model of the T800.

The transputer seems to meet all of Alan Steinburg's requirements. I'm sure
he is just unaware of certain vital facts about his competition.

Kenneth Reneris
{uw-beaver,decvax,sun,attunix,uunet}!microsof!kenr
DISCLAIMER: My opinions are my own, not those of my employer.