Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!ncar!husc6!necntc!ima!johnl
From: johnl@ima.ISC.COM (John R. Levine)
Newsgroups: comp.arch
Subject: Re: Press Release: Intel announces 80960 architecture
Message-ID: <949@ima.ISC.COM>
Date: 13 Apr 88 16:03:06 GMT
References: <3358@omepd> <10320@steinmetz.ge.com> <3363@omepd>
Reply-To: johnl@ima.UUCP (John R. Levine)
Organization: Not enough to make any difference
Lines: 20
Keywords: 80960, RISC, embedded control
Summary: An embedded processor with demand paging?

In article <3363@omepd> mcg@iwarpo3.UUCP (Steve McGeady) writes:
>>  4) what about memory management?
>... The 80960MC implements the 80960 ... and also includes an on-chip memory
>management unit which supports a standard virtual memory management system.
>... This processor is available in a mil-spec package, and is targeted at
>military and high-reliability embedded applications that require hardware
>protection of concurrent processes.

I would be fascinated to hear about high reliability embedded applications
that use virtual memory. Seems to me you'd need a pretty artful designer to
come up with a system that satisfies the sort of real-time constraints
generally present in embedded systems while handling page faults.

Or perhaps you could have a system with Unix, vi, and troff and X windows
burnt in so that fighter pilots can type up their reports on the way home from
a mission, using only an eye-tracking mouse equivalent built into the helmet.
And then send it home via uucp.  The possibilities are limitless.
-- 
John R. Levine, IECC, PO Box 349, Cambridge MA 02238-0349, +1 617 492 3869
{ ihnp4 | decvax | cbosgd | harvard | yale }!ima!johnl, Levine@YALE.something
Rome fell, Babylon fell, Scarsdale will have its turn.  -G. B. Shaw