Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!claris!apple!baum
From: baum@apple.UUCP (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: Press Release: Intel announces 80960 architecture
Message-ID: <7543@apple.UUCP>
Date: 13 Apr 88 16:43:56 GMT
References: <3358@omepd> <49265@sun.uucp>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 22

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[]
>In article <49265@sun.uucp> david@sun.uucp (David DiGiacomo) asks:
>>   The 80960KA and the 80960KB are both available in 20MHz CHMOS* III
>>configurations.  Both embedded processors operate at a sustained 7.5 MIPS
>>and 15K Dhrystones rates.
>
>Why is the integer performance so low?  Do most instructions take 2 cycles?

Actually, yes. Despite some fairly clever scoreboarding, many simple
instructions take two cycles. This appears to happen because they have a single
port register file. For example: A+B->C, D+E->F. The second addition will
take 2 cycles. But: A+B->C, C+E->F. The second addition will take 1 cycles.
This is because they forward the ALU result to the second addition, which
saves them a cycle. Ironic, since forwarding usually make instructions run
just as fast as they would if there were no data dependencies; here, data
dependencies make it run faster! 

NOTE: This is one PARTICULAR implementation. It is NOT an architectural
mis-feature. There are no architectural reasons why future versions shouldn't
run much faster (with the same clock rate).

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