Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!umd5!mimsy!chris
From: chris@mimsy.UUCP (Chris Torek)
Newsgroups: comp.arch
Subject: 80960 IO
Message-ID: <11067@mimsy.UUCP>
Date: 14 Apr 88 21:03:20 GMT
References: <3358@omepd> <10320@steinmetz.ge.com> <40@radix> <11026@mimsy.UUCP> <3368@omepd>
Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742
Lines: 17


>In article <11026@mimsy.UUCP> I said
>>IO space access is a bit muddy to me ...

In article <3368@omepd> mcg@omepd (Steven McGeady) answers:
>The 80960 has no special I/O - It is entirely memory mapped.  I/O registers
>(or whatever) can occur anywhere in the address space.

I was unclear in my unclarity.  I remember something about burst
mode memory access; if there is any sort of data cacheing in the
80960 architecture itself, one would need a way to inhibit multiword
reads from the bus during IO space references.

Of course, if data cacheing is to be done externally, this problem
vanishes (or rather, retreats into the board level).
-- 
In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 454 7163)
Domain:	chris@mimsy.umd.edu	Path:	uunet!mimsy!chris