Path: utzoo!utgpu!water!watmath!clyde!att-cb!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!pasteur!ucbvax!decwrl!pyramid!prls!mips!mark
From: mark@mips.COM (Mark G. Johnson)
Newsgroups: comp.arch
Subject: RISC floating point coprocessors
Message-ID: <2038@obiwan.mips.COM>
Date: 16 Apr 88 15:24:48 GMT
Reply-To: mark@mips.COM (Mark G. Johnson)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 36
Keywords:

In article <27292@yale-celray.yale.UUCP>, tam-hong@CS.Yale.EDU (Hong Tam) says
	> Does anyone know any references about the RISC architecture
	> with floating point co-processor?  I tried very hard but still
	> couldn't find any papers written about it.

One such architecture is the MIPS R2000, which dedicates "coprocessor 1"
to (IEEE compatible) floating point ..... it's implemented as a chip
called the R2010.  You can read about it in:
	Ries, Paul S., "An 8 MFLOP Floating-Point Coprocessor for a
	RISC Microprocessor", conference proceedings of IEEE Electro,
	10 May 1988.

Also, as dan@apple.UUCP (Dan Allen) pointed out in this newsgroup
<8306@apple.Apple.Com>,
	> .... [wait] until the next issue [of IEEE Micro] which is on
	> RISC stuff.
One of the papers in that issue (June 88) covers the FP coprocessor for
MIPS' newer CPU chip.

Other RISC FP coprocessor ideas:
	1. The IBM PC/RT uses a RISC processor and, I believe, a Motorola
	    MC68881 for floating point coprocessor.

	2. The Sun-4's use a Fujitsu gate array implementation of Sun's RISC
	   architecture (SPARC) for the CPU, and then a pair of standard
	   Weitek math chips for floating point.  A 2nd gate array controls
	   the Weitek chips & interfaces them to the CPU.  Don't know of
	   references, though.

	3. You might try digging around in the HP Technical Journal for
	   material on floating-point coprocessors for the Precision
	   (aka Spectrum) architecture.
-- 
 -Mark Johnson	*** DISCLAIMER: Any opinions above are personal. ***	
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