Path: utzoo!mnetor!uunet!husc6!bloom-beacon!mit-eddie!uw-beaver!apollo!mishkin
From: mishkin@apollo.uucp (Nathaniel Mishkin)
Newsgroups: comp.sys.apollo
Subject: Re: Does the Apollo DN10000 Exist?
Message-ID: <3b58860b.13422@apollo.uucp>
Date: 8 Apr 88 21:33:00 GMT
References: <1772@ssc-vax.UUCP> <8804012353.AA03028@pepper.sun.com> <1836@ssc-vax.UUCP>
Reply-To: mishkin@apollo.UUCP (Nathaniel Mishkin)
Organization: Apollo Computer, Chelmsford, MA
Lines: 64

I'm posting the following for Paul Bemis, Apollo Sr. Product Marketing
Manager:

------------------------------

The DN10000 is much more than a neat idea in someone's head!  The DN10000
hardware is up and running and its performance results are meeting (and
exceeding) expectations.

The DN10000 has separate instruction and data caches. The caches are
virtually indexed, physically tagged, write-through caches. This hybrid
design combines both the address translation/cache fetch parallelism
of a virtual cache with the cache coherency of a physical cache.  All
instructions, including LOAD and STORE, execute in a single cycle.

On the subject of multiprocessing and multiple threads, we use the OS
to spread multiple processes across multiple processors.  Thus for
process-rich applications, no modifications to the code are needed to
take advantage of a multi-processor configuration.  In addition, this
methodology works nicely as a work group shared compute resource running
multiple applications.

On the issue of dual Integer/FP processors:  Each CPU has both an Integer
and a Floating Point processor.  The FPU contains two math units, an
FP ALU and a multiplier.  The data paths from CPU to the instruction
and data caches are both 64 bits wide.  This allows PRISM to retire two
operations per cycle, one in the FP unit and one in the integer.  In
addition, the instruction set supports compound 5-operand instructions
that can exercise both FP functional units at once.  Thus, in one
instruction, an FP mult, FP add and an integer operation can be performed
-- potentially reading up to 6 source operands and writing up to 5
destination operands, in each of four processors, per cycle.  The integer
processor can do floating-point loads.  Thus, for vector operations such
as ax+b, the math can be computed by the compound instructions in the
FPU, while the IP does the loads.  For LINPACK, FFT, etc. -- and even
some real programs! -- the processor runs at nearly its peak bandwidth.
The FPU supports integer operations; in cases where it makes sense, the
FPU and IP can do integer operations in parallel.

On Mach:  Mach is being ported to the DN3000/4000 systems by The University
of Michigan.  The PRISM architecture is well-suited for running Mach
and we will be investigating getting Mach ported to it (of course).

I hope this satisfies your curiosity.  If you have any further questions,
detailed literature on the Series 10000 can be obtained from any Apollo
sales field office.

------------------------------

I'll add one comment of my own:  We (well, at least I) am sometimes in
a quandary about what sort of postings should be replied to.  This above
reply came only after a number of people got involved in deciding what,
if anything, should be said.  I think that in general, people should
take no response from Apollo on a particular topic to mean "It would
be improper to respond", or "We stand by what we've said in public
announcements", or "We can't respond without getting a zillion people
involved to decide whether it's OK to respond".  In such cases, all I
can suggest is that you talk to an Apollo sales office.

-- 
                    -- Nat Mishkin
                       Apollo Computer Inc.
                       Chelmsford, MA
                       {decvax,mit-eddie,umix}!apollo!mishkin