Path: utzoo!mnetor!uunet!husc6!bbn!rochester!PT.CS.CMU.EDU!IUS3.IUS.CS.CMU.EDU!ralphw
From: ralphw@IUS3.IUS.CS.CMU.EDU (Ralph Hyre)
Newsgroups: comp.sys.apple
Subject: Re: Some points and a request
Message-ID: <1313@PT.CS.CMU.EDU>
Date: 5 Apr 88 02:23:45 GMT
References: <5499@spool.cs.wisc.edu>
Sender: netnews@PT.CS.CMU.EDU
Organization: Carnegie-Mellon University, CS/RI
Lines: 33
Keywords: Apple // clone

In article <5499@spool.cs.wisc.edu> cad@speedy.cs.wisc.edu (Owner of VLSI software) writes:
>One more item:
>	I am planning to build an Apple //e clone
>that will run at 10 MHz (yes 10).  This should make for one
>respectable machine (1 MIP maybe).  It will probably slow to 1 MHz
>for I/O, and timing, and it's max. clock rate will be programmable
>in ten steps.
Well, everybody is still waiting for Zip chips, where are you going to
find a 10 Mhz 6502?  Can you still use DIP's and IC sockets at this speed?
I'd happily buy build a machine that I could understand and repair myself.
I recommend that you use a 12 Mhz 65816, and design it for 16M of directly
addressable memory.  For more //e compatibility, you'll probably want to
design AE's or Checkmate's 64K bank-switching stuff in.  Have you thought
about 24-bit address I/O slots?  (like PC AT slots) 
multimaster bus operation?  (AST has a spec for this for the AT bus)
(good for multiprocessing: 680X0 and 80X86 operations)

Keep the 65832 and virtual memory in
mind (even the 65816 has some capabilities for this.)

A GS 'clone' would be nicer, you might even get away with 
>	I am planning to have a very hard time designing the
>system and a harder time building it.  If you have ideas, or
>would like to hear mine, email me.
>	I will post my preliminary plans if there is interest.
>
>Chris Schumann				chris@leyden.cs.wisc.edu

-- 
					- Ralph W. Hyre, Jr.

Internet: ralphw@ius2.cs.cmu.edu    Phone:(412)268-{2847,3275} CMU-{BUGS,DARK}
Amateur Packet Radio: N3FGW@W2XO, or c/o W3VC, CMU Radio Club, Pittsburgh, PA