Path: utzoo!utgpu!water!watmath!clyde!att-cb!osu-cis!tut.cis.ohio-state.edu!bloom-beacon!athena.mit.edu!wesommer
From: wesommer@athena.mit.edu (William Sommerfeld)
Newsgroups: comp.arch
Subject: Re: RISC floating point coprocessors
Message-ID: <4683@bloom-beacon.MIT.EDU>
Date: 17 Apr 88 04:19:39 GMT
References: <2038@obiwan.mips.COM> <571@taux01.UUCP>
Sender: daemon@bloom-beacon.MIT.EDU
Reply-To: wesommer@athena.mit.edu (William Sommerfeld)
Organization: Massachusetts Institute of Technology
Lines: 26

In article <571@taux01.UUCP> amos@taux01.UUCP (Amos Shapir) writes:
>In article <2038@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>>	1. The IBM PC/RT uses ... a Motorola
>>	    MC68881 for floating point coprocessor.
>
>No, it uses NSC's 32081 FPU chip.

I claim that you're wrong.

The `APC' model PC/RT (the CMOS version which runs at roughly 3-4MIPS,
as opposed to the original dog which runs at 1.5MIPS) uses a 68881 FPU;
there is also an option for a higher performance `AFPA' unit.  When I
looked at the AFPA board, it appeared that it used one or more AMD
chips which I couldn't identify from memory.

The ACIS 4.3BSD for the RT logs the following on reboot:

Mar 20 01:33:12 snorkelwacker vmunix: AFPA marked down pending microcode load and initialization.
Mar 20 01:33:12 snorkelwacker vmunix: 68881 enabled.

By the way, this is being posted from a `slow'-model RT, which is at
least marginally faster than a MicroVAX II...

				Bill Sommerfeld
				MIT Project Athena.
				wesommer@athena.mit.edu