Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!decwrl!ucbvax!pasteur!ames!mailrus!husc6!linus!alliant!steckel
From: steckel@Alliant.COM (Geoff Steckel)
Newsgroups: comp.arch
Subject: MMU and/or external abort on 80376/80960?
Message-ID: <1599@alliant.Alliant.COM>
Date: 16 Apr 88 03:13:06 GMT
Reply-To: steckel@alliant.COM (Geoff Steckel)
Distribution: na
Organization: Omnivore Technology, Newton, MA
Lines: 57
Keywords: MMU multitasking BUSERROR

Do either of the new Intel chips support either limited or general
MMUs?  The press notes are contradictory on this point.  I know that
the '960-MC has some sort of fancy paging ability, but at $2000+ per,
it's moot.  I'm interested in the reduced 80386 (80376?) and the
non-militarized 80960s.

By 'support a MMU' I mean, using either on or off-chip MMU hardware:

1)
  Allow multitasking with process relocation (e.g. a flat address space
  for each process, with each process at 'logical 0 (or 0x20000 or...))

  Segment registers a la 8086 need not apply (:-).  Remember base regs
  on 360's?  If they must be used, can I set them all to 0 (or some such)
  and have a flat space?  Can they be used to avoid/alter access restrictions?
  (see 2 below)

2)
  Allow an OS or other supervisory software to arrange that a process
  will be suspended in a restartable state **before** a reference to
  memory or I/O resources is passed off-chip (for on-chip MMU) or
  beyond the off-chip MMU.  This supports demand paging.

  Failing the above, ability to have some method to probe a space in
  a predictable manner.  All other 'prohibited' references
  should be aborted, not necessarily in a continuable manner, but
  before any reference modifies any resource.

  This was the method used to run a 3-segment (code, data, stack) V7 UNIX
  on a 68000 with external MMU.  This version of Unix did not page, but
  swapped whole segments, and only required the stack to auto-extend.
  A sacrificial probe instruction was compiled in the standard subroutine
  prologue.  The OS checked all 'bus error' PCs for a 'tstb -n(FP)'
  and assumed that the 'n' was an implicit request to extend the stack.
  Grotesque, but it works.

  Failing all of the above (and just barely better than stone axes) (:-)
  an external signal which causes a non-restartable trap and aborts the
  current memory cycle before logical completion of the cycle or instruction.
  This is not the RESET line - I'd really like to know the error PC!
  This is for damage control - keepa you process offa my data! (:-)


This questions are not just 'can I run Unix/Mach/whatever on it?'
Most complex applications needing the power of a 32-bit CPU are multitasking
applications, even if they are simple ones.  No, you don't necessarily want
a multi-user system, but you DO want confidence that tasks can't clobber
each other.

Having used memory protection on a number of 'embedded control' applications
I found it reduces debugging effort by weeks at a time.  Using 'NMI' or other
interrupt hackery just isn't enough (or doesn't work!).  For this reason I
specify 68000-family chips wherever possible for embedded applications.
The 'BUS ERROR' pin is just TOO useful.  It would be nice if Intel chips
could compete here.

	geoff steckel (steckel@alliant.COM)