Path: utzoo!mnetor!uunet!lll-winken!lll-crg.llnl.gov!brooks
From: brooks@lll-crg.llnl.gov (Eugene D. Brooks III)
Newsgroups: comp.arch
Subject: Sofware cache control for RISC chip sets
Message-ID: <6258@lll-winken.llnl.gov>
Date: 17 Apr 88 20:58:57 GMT
Sender: usenet@lll-winken.llnl.gov
Reply-To: brooks@lll-crg.llnl.gov (Eugene D. Brooks III)
Organization: Lawrence Livermore National Laboratory
Lines: 23

Now that the super duper high performance RISC chip sets are being dumped
upon us  (I guess dumped is poor word, as we are eagerly awaiting them),
some with seperate single chip code and data caches, can anyone
provide some information on what type of cache control mechanisms these
processor architectures provide?  In bus based shared memory multiprocessors
one can have cache coherence managed with good efficiency, but modest numbers
of the latest hotrods seem to be quite capable of saturating any reasonable
bus even with coherent copy/back caches.

One eventually will want to move on to "non bus" shared memory subsystems
where setting up an automatic cache coherence scheme is far more difficult.
Using software cache control, where loads and stores are generalized with
several cache options attached to each, for instance "plain load (from
cache if its there)", "load replacing the cache line with a fresh line from
memory", ...; "store (only in cache if its there)", "store writing through the
cache to main memory leaving the value in cache", "store writing though the
cache to main memory, dumping the line", etc ,etc.

Such custom cache operations look a lot like register management, and I am
quite a proponent for forgetting the cache, having LOTS of registers, and
pipelining all memory accesses.  Anyway, as long as the processors have a
limited register file we will need the cache, and we need to have some
way of managing the cache with an intellegent compiler.  So what type of
cache control is supported by the new micros?