Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!mailrus!husc6!bloom-beacon!mit-eddie!uw-beaver!ssc-vax!benoni
From: benoni@ssc-vax.UUCP (Charles L Ditzel)
Newsgroups: comp.arch
Subject: Re: RISC floating point coprocessors
Message-ID: <1863@ssc-vax.UUCP>
Date: 18 Apr 88 02:06:41 GMT
References: <2038@obiwan.mips.COM>
Organization: Boeing Aerospace Corp., Seattle WA
Lines: 21

In article <2038@obiwan.mips.COM>, mark@mips.COM (Mark G. Johnson) writes:
> In article <27292@yale-celray.yale.UUCP>, tam-hong@CS.Yale.EDU (Hong Tam) says
> 	> Does anyone know any references about the RISC architecture
> 	> with floating point co-processor?  I tried very hard but still
> 	> couldn't find any papers written about it.
> 
> 	2. The Sun-4's use a Fujitsu gate array implementation of Sun's RISC
> 	   architecture (SPARC) for the CPU, and then a pair of standard
> 	   Weitek math chips for floating point.  A 2nd gate array controls
> 	   the Weitek chips & interfaces them to the CPU.  Don't know of
> 	   references, though.

Actually, Electronic News of March 21 page 23 talks about a "Coprocessor
From TI Aimed at SPARC".  "The SN74ACT8847 was designed to be used with
a number of CISC devices as well...Combining floating point and integer
capabilities, the 8847 is said to perform 30 Mflops in single and double
precision operations. "

I know zero about this...just what I have read...thought i'd pass it on.
---------------
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