Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!think!husc6!linus!sid
From: sid@linus.UUCP (Sid Stuart)
Newsgroups: comp.arch
Subject: Re: Press Release: Intel announces 80960 architecture
Message-ID: <29454@linus.UUCP>
Date: 18 Apr 88 11:43:58 GMT
References: <3358@omepd>
Reply-To: sid@linus.arpa (Sid Stuart)
Organization: The MITRE Corporation, Bedford MA
Lines: 17
Keywords: 80960, RISC, embedded control


>   The highly-integrated 80960KB has a number of functions on-chip that
>are characteristic of multiple-chip solutions.  On-chip functions include
>32 32-bit registers, the FPU [with four additional 80-bit registers],
>a 512-byte instruction cache, a stack frame cache, and a 32-bit multiplexed
>burst bus.			^^^^^^^^^^^^^^^^^?

	I have a copy of the 80960 Programmer's Reference Manual. I
can find no reference in it to a "stack frame cache". Can someone point
out where this is mentioned and what size this mythical cache is? Are the
four sets of local registers supposed to be the stack frame cache? 

sid@linus.arpa

BTW

I would like to thank Mr. McGeady for his timely posting of the
Intel press release.