Path: utzoo!mnetor!uunet!husc6!bloom-beacon!tut.cis.ohio-state.edu!mailrus!nrl-cmf!ames!lll-tis!mordor!sri-spam!sri-unix!garth!walter
From: walter@garth.UUCP (Walter Bays)
Newsgroups: comp.arch
Subject: Re: Sofware cache control for RISC chip sets
Message-ID: <605@garth.UUCP>
Date: 18 Apr 88 17:46:42 GMT
References: <6258@lll-winken.llnl.gov>
Reply-To: walter@garth.UUCP (Walter Bays)
Organization: INTERGRAPH (APD) -- Palo Alto, CA
Lines: 35

In article <6258@lll-winken.llnl.gov> brooks@lll-crg.llnl.gov (Eugene D. Brooks III) writes:
>Now that the super duper high performance RISC chip sets are being dumped
>upon us  (I guess dumped is poor word, as we are eagerly awaiting them),
>some with seperate single chip code and data caches, can anyone
>provide some information on what type of cache control mechanisms these
>processor architectures provide?  In bus based shared memory multiprocessors
>one can have cache coherence managed with good efficiency, but modest numbers
>of the latest hotrods seem to be quite capable of saturating any reasonable
>bus even with coherent copy/back caches.

The Clipper supports non-cached, write-through, and copy-back modes
per virtual memory page.  They are set by writing the CAMMU (cache and
memory management unit) control register.  (The I-CAMMU performs instruction
pre-fetch, so the instruction hit rate is very high.)

Under CLIX (UN*X System V) the three cache modes can be specified by
ld(1) per text, data, and stack segments.  Default mode is copy-back.
For very large programs with poor locality of reference, write-through
can actually be a bit faster for the data segment.  Depending on
reference patterns, you might want to use write-through for
multi-processors.

The bus would saturate with more than a few Clippers, and that gets to
the conjecture in your note.  Non-bus architectures may be needed for
very fast multi-processors.  Many RISC processors expose the pipeline
for compiler control.  Are there any processors that expose the cache
for compiler control, and would that be useful for hypercubes?
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