Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!pyramid!csg From: csg@pyramid.pyramid.com (Carl S. Gutekunst) Newsgroups: comp.arch Subject: Re: Proposed architecture characterization survey form Message-ID: <20123@pyramid.pyramid.com> Date: 19 Apr 88 20:23:13 GMT References: <2048@gumby.mips.COM> <49983@sun.uucp> Organization: Pyramid Technology Corp., Mountain View, CA Lines: 50 In article <49983@sun.uucp> ram@sun.UUCP (Renu Raman) writes: >Commercial > > Pyramid: 90X Also Pyramid 9810, same architecture. It has been debated whether the Pyramid architecture is "really" RISC, since it has a rather bulky instruction set, microcode, an interlocked pipeline, and instructions you'll never find on a CPU designed by John Hennessey (like interruptable block move). On the other hand, it *did* borrow liberally from RISC I and MIPS-X, the most visible ele- ments being the sliding register window for function calls, and the notion of using smart compilers instead of smart hardware. The 90x and 9810 both use a schottky TTL implementation, but that is strictly an implementation issue. One other commercial RISC: Celerity 1200, et al What is ironic is that Celerity's product literature has been very low-key about its RISC architecture, though the 1200 is more "RISC" than either Ridge or Pyramid, the two vendors who were making the most noise about RISC at the time the 1200 was announced. The machine's floating point performance scaled well with its integer performance, something only a few other processors have demonstrated (e.g. the MIPS R2000). > Apollo: The *system* has been announced as the Apollo 10000. Sun's salespeople have been making derisive noises about it, since Apollo announced the box before two of its eight (six? ten?) gate arrays had seen silicon. Actually, announcing processors that have only been simulated has become commonplace. This is almost reasonable, given the quality of simulation tools available these days. > DEC: ??? DEC's big RISC engine goes by the code name "Titan." It is something around 10 MIPS, up to 10 tightly-coupled CPUs. It's supposed to be a big secret, so don't spead this around. :-) A mildly interesting point is the success of commercial RISC products that have been in the marketplace for a while. Ridge and Celerity are essentially in the past tense, although Ridge is still tying to make a go of it. Pyramid is thriving. The IBM PC/RT was a flop. The MIPS R2000 has done fairly well, although I've been surprised by the number of vendors jumping on top of SPARC when the R[23]000 has so much more going for it. (Save the flames, I've read all the debates on this.) The SPARC is too new to call, but it appears that it will be a smashing success.