Path: utzoo!mnetor!uunet!tektronix!tekcrl!tekgvs!larryh
From: larryh@tekgvs.TEK.COM (Larry Hutchinson)
Newsgroups: comp.arch
Subject: Re: 80960 IO
Message-ID: <3364@tekgvs.TEK.COM>
Date: 19 Apr 88 15:54:45 GMT
References: <3358@omepd> <10320@steinmetz.ge.com> <40@radix> <11026@mimsy.UUCP> <3368@omepd> <11067@mimsy.UUCP> <3385@omepd>
Reply-To: larryh@tekgvs.UUCP (Larry Hutchinson)
Organization: Tektronix, Inc., Beaverton,  OR.
Lines: 23

In article <3385@omepd> mcg@iwarpo3.UUCP (Steve McGeady) writes:
>
>I should have tried to understand more thoroughly.  The existing
>implementations do no data caching per se (other than the stack frame register
>cache).  Therefore, the burst mode bus is not a problem.

Caching is not the only problem with I/O devices.  It is (was?) common
practice for status registers to be cleared upon being read.  Thus burst
mode is a no-no with such registers.

>memory waitstate (7% typical).  This is much lower than many competing
>processors, and makes it practical to build 80960 systems without
>expensive and board-space-consuming caches.  Another reason why the 80960
>is targeted at a controller market, as opposed to a system market.
>

Right!  And I suppose you have some swamp land to sell us too! :-)


Larry Hutchinson, Tektronix, Inc. PO Box 500, MS 50-383, Beaverton, OR 97077
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