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From: butcher@G.GP.CS.CMU.EDU (Lawrence Butcher)
Newsgroups: comp.arch
Subject: Re: Proposed architecture characterization survey form
Message-ID: <1468@pt.cs.cmu.edu>
Date: 20 Apr 88 05:49:45 GMT
References: <2048@gumby.mips.COM> <49983@sun.uucp>
Sender: netnews@pt.cs.cmu.edu
Organization: Carnegie-Mellon University, CS/RI
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When is a RISC not a RISC?  Today I got copies of the 80960KB Programmer's
and Hardware Designer's reference manuals.  32 AND 64 bit instructions.
Enthusiastic addressing modes.  Multiple-cycle instructions.  Confused
call/return instructions.  Decimal data type.  Trig functions in microcode
instead of manufacturer-sanctioned subroutines.  No delayed branching.
Zero-cycle branches anyway by making other instructions SO SLOW that the
branch is finished before the previous instruction is done.  Multiplexed
address/data bus.  No memory management.  No support for page faults.
Maximum instruction time 75878 clocks +- 40%. (probably typo :-)

Maybe the 8087 is a RISC?  But really Intel does not advertise this chip
as a RISC.  They have target the "embedded-processor" market.  The KB chip
doesn't suggest workstations to me.  I had hoped that this chip would help
AMD, Motorola, and MIPS revise the price of their chip sets downword.
Maybe next one, Intel?  :-)

Weitek has a family of processors called the XL-8000/XL-8032/XL-8064.  I
don't think that they are advertised as being RISC, but I think that they are.
The 3 chip set contains no memory management, but can deal with page faults.
The architecture has seperate instruction address, 64 bit instruction data,
data address, and 32 or 64 bit data busses.  At most an integer instruction,
a floating point multiply-accumulate, and a short conditional branch can be
executed each clock.  A complete cross-development system is available.  The
set comes 8 MHz, 10 MHz, and 12 MHz.  The 8 MHz part dhrystones around 6500,
I think.  It is MUCH faster at floating point than that number suggests.

Let me point out an article that might be interesting to readers.  The
Volume 16 Number 1 March 1988 issue of Computer Architecture News has an
article by Wm. A. Wulf on "The WM Computer Architecture".  Wulf has a
background in compiler-design and has a very good idea of what instruction
sequences occur in real code.  He describes a RISC instruction set with
32-bit instructions which name 3 source registers and 2 alu operations
per instruction.  He argues that the compiler can juggle ALU ops so that
the second operation frequently does useful work.  His machine transfers
instructions to the Integer ALU and Floating Point ALU thru fifo's,
condition codes from the ALUs to the IFU thru fifo's, and data to and
from memory thru fifo's.

This thing seems like a step in the direction of a RISC VLIW.  If things
like page faults were figured out, and if interrupts could happen without
causing registers to be overwritten before being used, and if delayed
branching really wasn't important as claimed, and if the ALU ops were
simple (only one ALU could multiply or divide), would this instruction
set really be 2 or more times faster than today's RISCs at the same speed
for roughly the SAME cost?  Would it be as economical for a conventional
RISC to fetch 2 instructions at the same time and execute them in parallel
if there were no data dependency??