Path: utzoo!mnetor!uunet!husc6!purdue!decwrl!granite!allen
From: allen@granite.dec.com (Allen Akin)
Newsgroups: comp.arch
Subject: Re: Proposed architecture characterization survey form
Message-ID: <221@granite.dec.com>
Date: 20 Apr 88 17:52:31 GMT
References: <2048@gumby.mips.COM> <49983@sun.uucp> <20123@pyramid.pyramid.com>
Reply-To: allen@decwrl.dec.com (Allen Akin)
Organization: DEC Technology Development, Palo Alto, CA
Lines: 16
Keywords:


In article <20123@pyramid.pyramid.com> csg@pyramid.pyramid.com (Carl S. Gutekunst) writes:
>
>DEC's big RISC engine goes by the code name "Titan." It is something around 10
>MIPS, up to 10 tightly-coupled CPUs. It's supposed to be a big secret, so don't
>spead this around. :-)
>
><csg>

Just to clarify things for the masses:

Titan is a research RISC machine designed and implemented several years
ago by DEC's Western Research Lab in Palo Alto.  It's been mentioned in
a number of papers published by WRL (see Wall and Powell's paper in
ASPLOS II, for example) so feel free to spread it around. :-)

Allen