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From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Wulf's WM
Message-ID: <28200131@urbsdc>
Date: 19 Apr 88 16:47:00 GMT
Lines: 40
Nf-ID: #N:urbsdc:28200131:000:2120
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Apr 19 10:47:00 1988


I expected to see something here by now, but maybe I'll have to start
- wht do y'all think of the WM processor, as described in 
Computer Architecture News Vol 16 No 1, March 1988, "The WM
Computer Architecture", William Wulf. Normally CAN contains a lot
of crank articles, but when somebody like Wulf publishes there
you have to pay attention.

In brief, it is divided into Instruction Fetch Unit, Integer Execution
Unit, and Floating Execution Unit, IFU, IEU, and FEU. An instruction
may be dispatched to each of these units on a cycle; all instructions
are 32 bits, so the decoder is looking at 96 at a time.

Each IEU and FEU instruction is of the form A op (B op C), so you
could dispatch as many as 5 <operations> per cycle. The double op
is useful for inner products, range checks, etc. There is a dependency
rule that says that the result of one instruction is not seen at
the inner op of the next.

Condition codes are placed in a FIFO, and are taken off the FIFO 
when the IFU actually needs to branch. Similarly, LOAD and STORE
instructions deal with data from FIFOs, placed there by writing to 
R0 and/or R1, and reading from them. Address computation is decoupled
from generation of the data to be stored. You can, for example, set
up a stream of data from memory with only one instruction, and
thereafter access it with purely scalar ops.

As usual, many of these ideas have been seen before: FIFO load/stores
and CCs, the A op (B op C) in DSP processors. But they're put together
in a nice package here. Somebody who I very much respect says that
this is the most important paper in computer architecture since 
the early papers on RISC.

I'll be making subsequent postings in a little while about issues
WM brings out, eg use of FIFOs rather than register renaming, 
- remember Patterson's paper "What do you do with 1000 registers?".
Well, I think that we have gone past the point of diminishing
returns for number of registers (although maybe not for highly
parallel machines, eh Larry?), and now we have to think of something
else to do with land area. How about "What do you do with a dozen
ALUs?"