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From: agn@UNH.CS.CMU.EDU (Andreas Nowatzyk)
Newsgroups: comp.arch
Subject: Re: Wulf's WM
Message-ID: <1508@pt.cs.cmu.edu>
Date: 23 Apr 88 17:53:01 GMT
References: <28200131@urbsdc>
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Organization: Carnegie-Mellon University, CS/RI
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Wulf presented the WM architecture here at a recent CS seminar, and it
appeared like a very clean and efficient system. Most design decisions
were backed up with data gathered during his work on high quality
optimizing compilers and appeared to be sound.

Of particular appeal to me was the introduction of fifo's into the
load/store instructions (decoupling the time when an address is issued
from the time when the data is accessed) as it has the *potential*  of
allowing more latency in the memory system without degrading the throughput.

However, there are a few dark areas:

The WM generates a tremendous load on the memory system: In each cycle,
it can generate 9 memory references, half of which could be for more than
32 bit. It seems to me that this implies a multiported *virtual* cache.
Cache efficiency could be quite low as the stream-instruction are begging
to be used as a powerful, general purpose vector facility that has the
potential to sweep of large portions of the memory (caches don't help
too much if you are accessing a sizable fraction of the address space
periodically, as seen in scientific code).

The other dark area are exceptions/interrupts/pagefaults/context-swaps:
there is a lot of state in WM and there is a fair amount of asynchronicity
to be sorted out. Wulf entertained the notion of an imprecise exception
(of IBM 360/91 fame) that I don't find too attractive. However, I'm not
convinced that this is the only answer to this problem.

-- 
   --  Andreas Nowatzyk  (DC5ZV)

   Carnegie-Mellon University	     Arpa-net:   agn@unh.cs.cmu.edu
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