Path: utzoo!mnetor!uunet!husc6!bloom-beacon!tut.cis.ohio-state.edu!mailrus!ames!oliveb!sun!shukra!ram
From: ram%shukra@Sun.COM (Renu Raman (Sun Microsystems))
Newsgroups: comp.arch
Subject: Re: Wulf's WM
Message-ID: <50669@sun.uucp>
Date: 24 Apr 88 20:47:10 GMT
References: <28200131@urbsdc> <1508@pt.cs.cmu.edu>
Sender: news@sun.uucp
Reply-To: ram@sun.UUCP (Renu Raman (Sun Microsystems))
Organization: Sun Microsystems, Mountain View
Lines: 14

In article <1508@pt.cs.cmu.edu> agn@UNH.CS.CMU.EDU (Andreas Nowatzyk) writes:
>
>Of particular appeal to me was the introduction of fifo's into the
>load/store instructions (decoupling the time when an address is issued
>from the time when the data is accessed) as it has the *potential*  of
>allowing more latency in the memory system without degrading the throughput.
>
   This is not new.  Read about the ZS-1 in the prevous ASPLOS conference
   proceedings.  A real machine exists with queues/fifos as interface to
   the memory system.  For more details read "The ZS-1 Central Processor"
   by Smith et. al. ASPLOS - 87.
>
>   --  Andreas Nowatzyk  (DC5ZV)
>