Path: utzoo!mnetor!uunet!husc6!bloom-beacon!mit-eddie!bbn!rochester!pt.cs.cmu.edu!A.GP.CS.CMU.EDU!koopman
From: koopman@A.GP.CS.CMU.EDU (Philip Koopman)
Newsgroups: comp.arch
Subject: RISC != real-time control
Message-ID: <1521@pt.cs.cmu.edu>
Date: 25 Apr 88 17:15:53 GMT
Sender: netnews@pt.cs.cmu.edu
Organization: Carnegie-Mellon University, CS/RI
Lines: 43
Keywords: RISC, real-time


One aspect of RISC processors for real time control that I
have not seen discussed is the conflict between
deadline scheduling and the statistical nature of
RISC performance figures.

Real-time control programs often have a situation where only
X microseconds are available to perform a task.  Therefore,
the code to perform the task must be GUARANTEED to complete
within X microseconds.  In real-time control, a late answer
is a wrong answer.

The problem with RISC designs is that they promise a performance
of Y MIPS in the average case over large sections of code and
relatively long periods of time.  It seems to me that this
is not an applicable performance measure for real-time control.
What is more important is worst-case performance (maximum
possible cache misses for that program, branch-target buffer
misses, etc.)  It may be the case that a slower processor
with uniform performance can be rated at a higher usable
MIPS rate than a RISC processor with inconsistent
instantaneous performance.

So, what is a real-time control designer to do?

-- De-rate the RISC MIPS ratings to assume 100% cache misses?

-- Use (probably) non-existent tools to compute worst-case
   program execution time under all possible conditions?

-- Not use RISC in an environment with short deadline events?


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~  Phil Koopman             5551 Beacon St.             ~
~                           Pittsburgh, PA  15217       ~
~  koopman@faraday.ece.cmu.edu   (preferred address)    ~ 
~  koopman@a.gp.cs.cmu.edu                              ~
~                                                       ~
~  Disclaimer: I'm a PhD student at CMU, and I do some  ~
~              work for WISC Technologies.              ~
~              My opinions are my own, etc.             ~
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