Newsgroups: comp.arch
Path: utzoo!henry
From: henry@utzoo.uucp (Henry Spencer)
Subject: Re: RISC != real-time control
Message-ID: <1988Apr26.024724.6596@utzoo.uucp>
Keywords: RISC, real-time
Organization: U of Toronto Zoology
References: <1521@pt.cs.cmu.edu>
Date: Tue, 26 Apr 88 02:47:24 GMT

> So, what is a real-time control designer to do?

The same thing he does with a high-powered CISC:  swear loudly, try to
estimate worst-case performance, and contemplate going back to the Z80.
At least RISC instruction times are more or less predictable, unlike those
of, say, the 68020.

More generally, there is a fundamental clash between trying to make the
performance simple and predictable and trying to maximize it by exploiting
regularities in the workload.  If you want absolutely predictable speed,
then (for example) you will either have to live without caches or else
manage them very carefully so you know what they're doing.  The same applies
to optimizing compilers, buffered I/O devices, asynchronous buses, etc etc.
-- 
"Noalias must go.  This is           |  Henry Spencer @ U of Toronto Zoology
non-negotiable."  --DMR              | {ihnp4,decvax,uunet!mnetor}!utzoo!henry