Path: utzoo!mnetor!uunet!tektronix!reed!psu-cs!newsa
From: newsa@psu-cs.UUCP (News Administrator)
Newsgroups: comp.arch
Subject: Re: 80960 IO
Message-ID: <647@psu-cs.UUCP>
Date: 25 Apr 88 20:42:59 GMT
References: <3358@omepd> <10320@steinmetz.ge.com> <40@radix> <11026@mimsy.UUCP> <3368@omepd> <11067@mimsy.UUCP> <3385@omepd>
Organization: Dept. of Computer Science, Portland State University; Portland OR
Lines: 30
In-Reply-To: <3364@tekgvs.TEK.COM>



In article <3364@tekgvs.TEK.COM> Larry Hutchison explains that burst bus
accesses can screw up memory mapped I/O.  There is a basic confusion here.

Instruction fetches and prefetches are not what is at issue here, but for
completeness' sake:  The 80960 architecture allows burst fetches and
prefetches of instructions.  Note that the burst prefetch is required to be
implemented so that spurious page faults are not reported.  This is easy.

On data accesses, which is at issue here, the size of the data access is 1
byte, 2 bytes, 3 bytes, 4 bytes, 8 bytes, 12 bytes, or 16 bytes.  The size of
the access is determined by the instruction.  If the access is not aligned on
a natural boundary, a "split" access will occur.  All this is independent of
caching.

Architecturally speaking, one advantage of defining the wider instructions
is that it allows an implementation to easily exploit wider internal datapaths.

Some of the load instructions (ignoring the subword cases for now) are:
	ld	load 32 bits
	ldl	load 64 bits
	ldt	load 96 bits
	ldq	load 128 bits
There are matching store instructions.

Although it may not be obvious, significant experience coding with these
multi-word loads and stores has convinced me that they are useful instructions
to have.  Many data structures are small enough to be easily manipulated with
these instructions, without resorting to multiple instructions or to string
move instructions.