Path: utzoo!mnetor!uunet!ncc!alberta!cdshaw
From: cdshaw@alberta.UUCP (Chris Shaw)
Newsgroups: comp.arch
Subject: Re: Proposed architecture characterization survey form
Message-ID: <1235@pembina.UUCP>
Date: 26 Apr 88 03:26:22 GMT
References: <2048@gumby.mips.COM> <50070@sun.uucp> <2052@gumby.mips.COM> <219@granite.dec.com>
Reply-To: cdshaw@pembina.UUCP (Chris Shaw)
Organization: U. of Alberta, Edmonton, Alberta, Canada
Lines: 31
Keywords: RISC

In article <219@granite.dec.com> paulr@granite.UUCP (Paul Richardson) writes:
>RISC: 
>      1) A machine in which the instruction set is designed/chosen based
>         on what makes the most sense to put into the hardware....
>
>      2) ..a characteristic of RISC machines that they have a 'large'
>	 general purpose register file. ...
>/pgr

One of the 801 people (Blasgen) gave a talk here a while ago about 801, and 
the associated philosophy. Back then, what "Reduced" meant was "reduced
instruction time". That is, the design goals were to have the simplest 
instructions (nop/add/logic...) take one clock. Clearly, more complicated
stuff like multiply would take longer, but shortness of TIME was the main 
design goal.

Now, an ethic of this kind will lead a designer down a restricted design path:
Simple addressing, pipelines, caches, etc. If I recall right, the 801 was not 
a single-chip machine, so area restrictions did not apply (as much). Given that
the Berkeley and Stanford people wanted a single-chip CPU, the silicon area
restriction applies, so "Reduced" starts to mean "reduce the NUMBER of
instructions (so we can fit something useful on chip)".

I think that applying RISC to mean Reduced TIME is the only thing that makes
100% sense as a "commandment". Reducing NUMBER of instructions will probably
come out in the wash.

-- 
Chris Shaw    cdshaw@alberta.UUCP (via watmath, ihnp4 or ubc-vision)
University of Alberta
CatchPhrase: Bogus as HELL !