Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!oliveb!pyramid!prls!mips!larry
From: larry@mips.COM (Larry Weber)
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <2079@gumby.mips.COM>
Date: 26 Apr 88 01:57:49 GMT
References: <1521@pt.cs.cmu.edu>
Reply-To: larry@gumby.UUCP (Larry Weber)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 41
Keywords: RISC, real-time

In article <1521@pt.cs.cmu.edu> koopman@A.GP.CS.CMU.EDU (Philip Koopman) writes:
>
>One aspect of RISC processors for real time control that I
>have not seen discussed is the conflict between
>deadline scheduling and the statistical nature of
>RISC performance figures.
>
> ...
>So, what is a real-time control designer to do?
>
>-- De-rate the RISC MIPS ratings to assume 100% cache misses?
>
>-- Use (probably) non-existent tools to compute worst-case
>   program execution time under all possible conditions?
>
>-- Not use RISC in an environment with short deadline events?
>
Cache effects can be present in any machine that has a cache: CISC or RISC.  

Answer 1 will provide a general guide-line of the effect only if you 
know how YOUR application maps onto the MIPS rating.  Even if your
program followed the MIPS rating in a number of trials, you still have to
know how the time is allocated between memory references and other operations
which do not have a statistical nature.

Answer 2 will give a worst case bound on the performance.  The MIPS compilers
have tools that will inform you of the number cycles, instructions and 
memory references for a given run of the program.  Computing worst
case times is really a matter of multiplication.  This answer is
really over kill because not all applications require worst case times to be
used for every part of the problem.  For example, assume
you had to accept a piece of data and queue it for processing while
interupts were disabled.  The critical time is how long are interupts
disabled because data could be lost in that period.  

Answer 3 is like throwing out the baby with the bath water - this solution
should be generalized to any hardware that has a statistical nature.
This leaves out the 68020 and 030 too.
-- 
-Larry Weber  DISCLAIMER: I speak only for myself, and I even deny that.
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