Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!decwrl!purdue!i.cc.purdue.edu!j.cc.purdue.edu!pur-ee!uiucdcs!uiucdcsp!gillies
From: gillies@uiucdcsp.cs.uiuc.edu
Newsgroups: comp.arch
Subject: Re: RAM Question:
Message-ID: <76700023@uiucdcsp>
Date: 26 Apr 88 05:24:00 GMT
References: <1005@iitmax.UUCP>
Lines: 16
Nf-ID: #R:iitmax.UUCP:1005:uiucdcsp:76700023:000:643
Nf-From: uiucdcsp.cs.uiuc.edu!gillies    Apr 26 00:24:00 1988


There should be a more precise metric for machines with caches that
achieve zero wait-states.  For instance, if your machine is

Wait State		When			How often	
0			in the cache		97% of the time
2			not in the cache	3% of the time

Then I submit you are using a .06 wait-state machine.  The expected
value of the number of wait-states per memory reference is .06.  The
cache hit ratio should be computed by running a dhrystone benchmark
compiled in C, or some other "universal" benchmark.  Now maybe we can
get the PC companies to agree on this standard.....

Don Gillies {ihnp4!uiucdcs!gillies} U of Illinois
            {gillies@p.cs.uiuc.edu}