Path: utzoo!mnetor!uunet!husc6!bloom-beacon!gatech!udel!rochester!pt.cs.cmu.edu!A.GP.CS.CMU.EDU!koopman
From: koopman@A.GP.CS.CMU.EDU (Philip Koopman)
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <1532@pt.cs.cmu.edu>
Date: 26 Apr 88 15:39:39 GMT
References: <1521@pt.cs.cmu.edu>
Sender: netnews@pt.cs.cmu.edu
Organization: Carnegie-Mellon University, CS/RI
Lines: 41
Keywords: RISC, real-time
Summary: Clarification of the question

In article <1521@pt.cs.cmu.edu>, koopman@A.GP.CS.CMU.EDU (Philip Koopman) writes:
> One aspect of RISC processors for real time control that I
> have not seen discussed is the conflict between
> deadline scheduling and the statistical nature of
> RISC performance figures.
> [stuff deleted]

Thanks for the response so far.

I have received several replies of the form that any machine with
cache has problems with predictability of performance.
I agree, but that isn't the whole question/answer.  I thought
that RISCs had a higher cache miss rate (in misses per second,
not miss ratio) since they need more instructions, or is this
solved with increased line size/prefetching?

A better question is: is it appropriate to be using a RISC
on embedded applications?  What if you can't afford off-chip cache
memory -- doesn't the increased instruction bandwidth required
for a RISC cause problems?  I get the feeling that cache helps a CISC
somewhat, but that a RISC simply dies without a lot of cache -- is
that really the case?

Another concern has to do with program size.  Everything I've seen
says that RISCs have programs about twice as big as CISCs.  What
does that do in an embedded environment -- NO, Memory is NOT cheap
when it costs power/weight/cooling/volume/dollars/chip count in a highly
constrained application!

Thanks for the feedback,

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~  Phil Koopman             5551 Beacon St.             ~
~                           Pittsburgh, PA  15217       ~
~  koopman@faraday.ece.cmu.edu   (preferred address)    ~ 
~  koopman@a.gp.cs.cmu.edu                              ~
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~  Disclaimer: I'm a PhD student at CMU, and I do some  ~
~              work for WISC Technologies.              ~
~              (No one listens to me anyway!)           ~
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