Path: utzoo!mnetor!uunet!husc6!bloom-beacon!gatech!udel!rochester!pt.cs.cmu.edu!K.GP.CS.CMU.EDU!lindsay
From: lindsay@K.GP.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: Wulf's WM
Message-ID: <1533@pt.cs.cmu.edu>
Date: 26 Apr 88 16:07:03 GMT
References: <28200131@urbsdc> <1508@pt.cs.cmu.edu> <50669@sun.uucp> <7992@pur-ee.UUCP>
Sender: netnews@pt.cs.cmu.edu
Organization: Carnegie-Mellon University, CS/RI
Lines: 22

In article <7992@pur-ee.UUCP> hankd@pur-ee.UUCP (Hank Dietz) writes:
>Actually, it has been common for a while now.  I don't remember the model,
>but I know at least one of CSPI's array processors used FIFO interfaces not
>only to decouple memory references, but also to decouple interactions
>between control, address generation, and arithmetic hardware.

Yes, CSPI had such a machine in the mid-70's. They published about it, in
IEEE Computer (I think).  The address unit computed addresses and put them
into an address FIFO (FIFOs?). The data unit could load and store from a
pair of data FIFOs.

However, the CSPI machine was different from WM in that the two decoupled
units executed from two different instruction streams. Data-dependant
branching was not an option. This extreme decoupling was limited by the FIFO
depth (3 - to avoid fallthrough time). I believe that CSPI simulated the
architecture first, and were going for a win of about 2x speedup (on FFTish
problems).



-- 
	Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science