Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!amdahl!nsc!voder!apple!bcase
From: bcase@Apple.COM (Brian Case)
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <8974@apple.Apple.Com>
Date: 26 Apr 88 18:37:40 GMT
References: <1521@pt.cs.cmu.edu>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Apple Computer Inc, Cupertino, CA
Lines: 34
Keywords: RISC, real-time

In article <1521@pt.cs.cmu.edu> koopman@A.GP.CS.CMU.EDU (Philip Koopman) writes:
>One aspect of RISC processors for real time control that I
>have not seen discussed is the conflict between
>deadline scheduling and the statistical nature of
>RISC performance figures.

??????  And CISC (or whatever you consider an alternative to RISC) doesn't
have the so-called "statistical nature" of performance?!?!

>The problem with RISC designs is that they promise a performance
>of Y MIPS in the average case over large sections of code and
>relatively long periods of time.

??????  How do alternatives to RISC differ?

>What is more important is worst-case performance (maximum
>possible cache misses for that program, branch-target buffer
>misses, etc.)

Worst-case performance is always *most* important for real-time systems.
Because of fundamental limitations of technology (big DRAMs are slower
than small SRAMs), any processor that runs as fast as the technology will
allow will rely on caching to some degree (I claim).  To the extent that
your real-time code can't depend on the cache(s) containing your working
set (probably can't depend on it at all), you may be better off, in terms
of cost, designing the hardware without caches.  If the caches are on-chip,
then you have no choice of course.  Now, it *is* possible that, in an
environment where the cache(s) is(are) always missing, cache(s) will actually
make the system run slower.  However, it will be more and more difficult
to find any fast processor, CISC, RISC, or whatever-ISC, without on-chip
caches.  In fact, many CISCs will soon be implemented with a very RISC-
like core.  Oops, I guess I could have summarized this whole spiel by
simply saying "your problem isn't RISC, its statistical techniques in
general.  These techniques are universally used."  Maybe a good-old 68000
is your best bet?