Path: utzoo!mnetor!uunet!husc6!purdue!decwrl!granite!jmd
From: jmd@granite.dec.com (John Danskin)
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <226@granite.dec.com>
Date: 27 Apr 88 17:24:48 GMT
References: <1521@pt.cs.cmu.edu> <50884@sun.uucp>
Reply-To: jmd@granite.UUCP (John Danskin)
Organization: DEC Technology Development, Palo Alto, CA
Lines: 14
Keywords: RISC, real-time


We have a leetle teeny ucode engine (read risc by Weitek) that needs
some things locked into cache (a real time constraint that involves
the bus hanging if we slip by even one cycle (our fault, not
weitek's)).  Fortunately, our system uses direct mapped caches, so we
changed the linker so that modules which should be locked into
cache get unique addresses (modulo the cache size). This works
just fine, and since we have hardly any of this critical code, caused
only a 2% overall code growth (because of all of the little holes)
-- 
John Danskin				| decwrl!jmd
DEC Technology Development		| (415) 853-6724 
100 Hamilton Avenue			| My comments are my own.
Palo Alto, CA  94306			| I do not speak for DEC.