Path: utzoo!mnetor!uunet!husc6!mailrus!tut.cis.ohio-state.edu!rutgers!mtunx!mtune!petsd!pedsga!bob
From: bob@pedsga.UUCP
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <558@pedsga.UUCP>
Date: 27 Apr 88 12:19:19 GMT
References: <1521@pt.cs.cmu.edu>
Reply-To: bob@pedsga.UUCP (Bob Weiler,7343)
Organization: Concurrent Computer Corp., Tinton Falls, N.J.
Lines: 18
Keywords: RISC, real-time
Summary: Should work fine.

In article <1521@pt.cs.cmu.edu> koopman@A.GP.CS.CMU.EDU.UUCP writes:
> { questioning the suitability of RISC processors for Real-Time use }
> ...

It seems to me that it is much *easier*  to predict worst
case performance for RISC processors because

1) Most execute one instruction/clock. You don't have to figure
	out how many cycles each instruction actually takes.
2) Most don't have interuptible instructions. Who knows how
	long it takes?

If you are really concerned about cache misses, you would design
your system so that all the memory was fast enough for the processor.
And you wouldnt do demand-paging either.

Just my opinion.
Bob Weiler.