Path: utzoo!mnetor!uunet!pcrat!rick
From: rick@pcrat.UUCP (Rick Richardson)
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <476@pcrat.UUCP>
Date: 30 Apr 88 21:03:08 GMT
References: <1521@pt.cs.cmu.edu> <1532@pt.cs.cmu.edu>
Reply-To: rick@pcrat.UUCP (Rick Richardson)
Organization: PC Research, Inc., Tinton Falls, NJ
Lines: 29
Keywords: RISC, real-time

In article <1532@pt.cs.cmu.edu> koopman@A.GP.CS.CMU.EDU (Philip Koopman) writes:
>
>A better question is: is it appropriate to be using a RISC
>on embedded applications?  What if you can't afford off-chip cache
>memory -- doesn't the increased instruction bandwidth required
>for a RISC cause problems?  I get the feeling that cache helps a CISC
>somewhat, but that a RISC simply dies without a lot of cache -- is
>that really the case?
>

I'm still looking for the RISC that does ~4K (C language) Dhrystones,
has no cache, clocks around 4 Mhz, has a 16 bit bus, can address maybe 1MB,
is a power miser, can't do floating point, and costs no more than $15.

In HUGE quantities.  Just think of the millions and millions of next
generation consumer products that could use the extra performance,
while still meeting EMI, power consumption, and cost requirements.

Come on guys, I know that there's a lot of prestige in
having the fastest micro-* around, but theres a LOT of HIGH VOLUME
applications out there that just can't use all that power.

You might sell 10K-100K of these super high performance chips.
Wouldn't you rather sell *tens of millions*?
-- 
		Rick Richardson, President, PC Research, Inc.

(201) 542-3734 (voice, nights)   OR     (201) 834-1378 (voice, days)
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