Path: utzoo!lsuc!ncrcan!ziebmef!mcp
From: mcp@ziebmef.UUCP (Marc Plumb)
Newsgroups: comp.arch
Subject: Re: Proposed architecture characterization survey form
Summary: Transputers RISCish?????
Message-ID: <358@ziebmef.UUCP>
Date: 29 Apr 88 05:29:49 GMT
References: <2048@gumby.mips.COM> <3100001@hpmwtla.HP.COM>
Reply-To: mcp@ziebmef.UUCP (Colin Plumb)
Organization: Ziebmef Public Access Unix/BBS
Lines: 26
Confusion: Ziebmef Public Access BBS/Unix

garyb@hpmwtla.HP.COM (Gary Bringhurst) writes:

>Why has no one mentioned the Inmos Transputers?  They are certainly Risc'ish.

Sigh...

Is a processor with message passing, time-slicing, and context-switching
in microcode a RISC?  I honestly don't know where the Transputer belongs,
but 3 registers is a bit of a change from traditional RISC architectures.

The Transputer is a RISC in the "Relegate Important Stuff to Compiler"
sense - the amount of useful stuff that's been stripped from the instruction
set on the grounds that it can be implemented in terms of existing
instructions is astounding.  For example, since the Transputer considers
any non-zero value to be true, the magnitude comparison operations have
been reduced to signed greater-than, subtraction (zero result means equal
inputs) and "equal to constant", which can be used with a zero argument
to implement logical not.

Sufficient, certainly (it's turing-equivalent), but pleasant to use??

Sorry to go on, but the RISCiness of Transputers is a fabrication of
buzzword-happy marketroids, and I wouldn't want them to delude reasonably
sane people.
--
	-Colin (ncrcan!ziebmef!mcp)