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From: hankd@pur-ee.UUCP (Hank Dietz)
Newsgroups: comp.arch
Subject: Re: SPARC and multiprocessing
Message-ID: <8029@pur-ee.UUCP>
Date: 1 May 88 14:56:46 GMT
References: <1521@pt.cs.cmu.edu> <28200135@urbsdc> <4921@bloom-beacon.MIT.EDU> <51409@sun.uucp>
Organization: Purdue University Engineering Computer Network
Lines: 19
Summary: What about BIG multiprocessors?

I hate to add to this pile of news, but why hasn't anyone talked about the
fact that processors like SPARC are not really designed for large-scale
multiprocessing, e.g., they have no provision for "hiding" big, stochastic,
memory reference delays across a log n stage interconnection network, etc.?
I think it's pretty uninteresting to talk about multi-processor systems
which are small enough that "snooping caches" work; as many of you have
pointed-out, that's been essentially a non-problem for quite some years.
How about some discussion of what processors do when simple cache protocols
aren't good enough or are not implementable?

It seems we nearly got into such a discussion when WM was brought up, but WM
isn't really billed as being a processor design for large-scale
multiprocessors (read MIMDs), hence people didn't seem to notice that it was
addressing the stochastic delay memory reference problem so endemic to big
MIMDs.  Consider all those other processors with microtasking or other
out-of-order or multiple-memory-pipeline structures.  Anyone care to get a
discussion along these lines going?

						-hankd