Path: utzoo!mnetor!uunet!vsi!friedl
From: friedl@vsi.UUCP (Stephen J. Friedl)
Newsgroups: comp.lang.c
Subject: Re: volatile isn't necessary, but it's there
Message-ID: <548@vsi.UUCP>
Date: 16 Apr 88 01:30:01 GMT
References: <7794@alice.UUCP> <48767@sun.uucp> <144@obie.UUCP>
Organization: V-Systems, Inc. -- Santa Ana, CA
Lines: 29

In article <144@obie.UUCP>, wes@obie.UUCP (Barnacle Wes) writes:
> In article <48767@sun.uucp>, guy@gorodish.Sun.COM (Guy Harris) writes:
> | It is worth noting, for example, that there is no guarantee that "++mutex"
> | is an atomic operation.
> | [SPARC uses three instructions: load+inc+store]
> 
> Another good reason NOT to use a SPARC for anything other than a
> paperweight.  On a reasonable processor like the M68000, `++mutex'
> becomes an atomic operation like `addq #1,mutex'.

     A single instruction is no guarantee of atomicity either.
The VAX allows an increment instruction -- "INC mutex" -- but it
is not necessarily atomic; you need ADAWI (Add Aligned Word,
Interlocked) for that.  The VAX provides a half a dozen
instructions like this, designed for synchronized shared access,
and the docs say they are needed.  The WE32100 (in the AT&T 3B2)
has SWAPBI (swap bytes interlocked) instructions to do the same
kind of thing, so I surmise that instructions are not atomic
either.

     I know nothing about how the Moto works, but with today's
high-performance pipelined processors sharing memory with so many
kinds of other processors (DMA, I/O, math, etc.), relying on all
instructions being atomic is probably naive; it will just be
harder to track down where the mutex bugs are.

-- 
Steve Friedl   V-Systems, Inc.   "Yes, I'm jeff@unh's brother"
friedl@vsi.com  {backbones}!vsi.com!friedl  attmail!vsi!friedl