Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!amdahl!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.lang.c
Subject: Re: volatile isn't necessary, but it's there
Message-ID: <21242@amdcad.AMD.COM>
Date: 20 Apr 88 17:31:34 GMT
References: <7794@alice.UUCP> <48767@sun.uucp> <144@obie.UUCP> <2182@frog.UUCP>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Organization: Advanced Micro Devices
Lines: 13

In article <2182@frog.UUCP> john@frog.UUCP (John Woods, Software) writes:
| In article <144@obie.UUCP>, wes@obie.UUCP (Barnacle Wes) writes:
| I would be interested to know how one does multi-processor locking on a
| SPARC, however (or other RISC processors).  Anyone who *knows* care to
| comment?

The Am29000 has a "loadset" instruction, which loads a register from a
memory location, then sets that memory location to all-ones.  This
sequence is non-interruptable, and the *LOCK pin is asserted throughout
the entire transaction.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amdcad.amd.com)