Path: utzoo!mnetor!uunet!husc6!bloom-beacon!mit-eddie!uw-beaver!tektronix!sequent!mntgfx!mbutts
From: mbutts@mntgfx.mentor.com (Mike Butts)
Newsgroups: comp.arch
Subject: Re: SPARC and multiprocessing
Message-ID: <1988May2.095624.306@mntgfx.mentor.com>
Date: 2 May 88 16:56:19 GMT
References: <1671@alliant.Alliant.COM>
Organization: Mentor Graphics Corporation, Beaverton Oregon
Lines: 28

From article <1671@alliant.Alliant.COM>, by jeff@Alliant.COM (Jeff Collins):
> 
> 	Given that the SPARC must use a virtual cache to get optimal
> 	performance, how does one build a multiprocessor with a SPARC?
> 
> 	As far as I know, no one has solved the virtual cache coherency
> 	problem yet...
> 

Here's another log for the fire... Apollo says in their marketing booklet about
the new DN10000 architecture (which has 1 to 4 15-MIPS-RISC processors sharing
main memory):

"...the Series 10000's caches incorporate the best features of both fully physical
and fully virtual caches.  The result is a new *virtually indexed, physically 
tagged write-through cache* that lets cache RAM access proceed entirely overlapped
in time with any virtual-to-physical address translation.  This overlap reduces
memory access pipeline depth, guaranteeing single-cycle execution and eliminating
the translation penalty typical with physically indexed designs.

The physical tags allow cache validation across processors.  The addressing
scheme, based on the virtual address coupled with the physical tag, maintains
coherency and allows data to be shared by multiple processors."
-- 
Mike Butts, Research Engineer         KC7IT           503-626-1302
Mentor Graphics Corp., 8500 SW Creekside Place, Beaverton OR 97005
...!{sequent,tessi,apollo}!mntgfx!mbutts OR  mbutts@pdx.MENTOR.COM
These are my opinions, & not necessarily those of Mentor Graphics.