Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!sun!decwrl!purdue!i.cc.purdue.edu!j.cc.purdue.edu!pur-ee!uiucdcs!uxc.cso.uiuc.edu!urbsdc!aglew
From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <28200137@urbsdc>
Date: 1 May 88 00:15:00 GMT
References: <1521@pt.cs.cmu.edu>
Lines: 17
Nf-ID: #R:pt.cs.cmu.edu:1521:urbsdc:28200137:000:690
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Apr 30 19:15:00 1988


>As far as I know, no one has solved the virtual cache coherency
>problem yet...

There sure are a lot of folk who think they have, though not
commercially (yet). The virtual cache consistency problem is just
like the physical cache consistency problem, except that you
need a physical index for bus snooping.

[Knowing I'm gonna get flamed :-) ]: of course, Alliant doesn't
have too much to do with cache consistency - after all, the CEs
talk to the same cache, don't they, so don't have any consistency
problems? But how far can this scale? I suppose that the IPs
have to be kept coherent, and I believe that's writeback, but
the duty cycle doesn't have to be very high.

aglew@gould.com