Path: utzoo!utgpu!water!watmath!clyde!gwu
From: gwu@clyde.ATT.COM (George Wu)
Newsgroups: comp.arch
Subject: Re: Comp. Architecture & Organization (the class)
Summary: Carnegie-Mellon's comp.arch course.
Keywords: course texts, fundamental topics/issues
Message-ID: <25750@clyde.ATT.COM>
Date: 2 May 88 17:39:47 GMT
References: <3952@medusa.cs.purdue.edu> <1665@alliant.Alliant.COM>
Reply-To: gwu@clyde.UUCP (George Wu)
Distribution: na
Organization: AT&T Bell Laboratories, Whippany NJ
Lines: 48


     And now for a view from the other end of the spectrum, here's what
Carnegie-Mellon taught me. The architecture class per se was taught by
Dan Siewiorek. The text was "Computer Organization," by Hamacher, Vranesic,
and Zaky.

     First off, this is really the middle class in a series. It assumed
a basic digital logic class had al;ready been completed, and further assumed
an additional class (in microprogramming/bit slice design) would be
forthcoming.

     The actual architectures we studied were the PDP-8, PDP-11, VAX, and
MC68000. These machines were used to illustrate the following overall
topics: instruction formats/sets, arithmetic CPU operations, I/O, floating
point arithmetic, memory (including caches, translation buffers, and virtual
memory), bus architectures, 1/2/3 address machines, and a few other things
I don't recall.

     In depth knowledge of the MC68000 and PDP-11 was expected, via programming
assignments (ISPS simulator used for the latter). Other major projects included
simulating a cache with varying set, line, and overall sizes and replacement
algorithms. We also designed an instruction set and implemented it in ISPS
(a general purpose simulator).

     The following year, the class had much the same curriculum, but projects
included assembly-level code on somewhat simplified versions of Berkeley's RISC
and the MIPS machine as well. (Again, ISPS used to simulate those processors.)
Students also designed the hardware and microcode for part of the PDP-11,
instead of designing their own architecture. I believe it was the memory/bus
area, though I can't recall. (I had TA'ed an earlier part of the course, but
really wasn't involved with this part of the course.)

     The amount of actual hardware knowledge imparted was fairly low. Concepts
were stressed more than hardware. This was with the knowledge that seniors
would be taking Logic and Processor Design, in which they had to design,
build (hand wire-wrap), microcode, and debug (AARRGGHH!!) a Am2903 bit slice
based machine (two slices minimum).

-- 
					George J Wu

UUCP: {ihnp4,ulysses,cbosgd,allegra}!clyde!gwu
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-- 
					George J Wu

UUCP: {ihnp4,ulysses,cbosgd,allegra}!clyde!gwu
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