Path: utzoo!mnetor!uunet!lll-winken!lll-lcc!ames!ncar!boulder!sunybcs!bingvaxu!leah!itsgw!imagine!pawl18.pawl.rpi.edu!jesup
From: jesup@pawl18.pawl.rpi.edu (Randell E. Jesup)
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <833@imagine.PAWL.RPI.EDU>
Date: 3 May 88 08:01:20 GMT
References: <1521@pt.cs.cmu.edu> <1532@pt.cs.cmu.edu> <476@pcrat.UUCP>
Sender: news@imagine.PAWL.RPI.EDU
Reply-To: jesup@pawl18.pawl.rpi.edu (Randell E. Jesup)
Organization: RPI Public Access Workstation Lab - Troy, NY
Lines: 21
Keywords: RISC, real-time

In article <476@pcrat.UUCP> rick@pcrat.UUCP (Rick Richardson) writes:
>I'm still looking for the RISC that does ~4K (C language) Dhrystones,
>has no cache, clocks around 4 Mhz, has a 16 bit bus, can address maybe 1MB,
>is a power miser, can't do floating point, and costs no more than $15.

	Yeah, and what technology is this wonder-chip implemented in???
Whatever it is, I can think of dozens of Si companies that would give away
all their current facilites for that process.  Oh, and I'm not even worrying
about cost.

	Back to reality, it just can't be done, except MAYBE with a state of
the art chip optimized to NOTHING but fast dhrystones (which, by the way,
are a pretty poor predicter for most applications, due to string handling.)
4 Mhz is REAL slow.  A 4Mhz rpm-40 would be equivalent to maybe a 14Mhz
68000 (note: not '020).  At such slow speeds, CISC chips may well show
superiority due to wanting to maximize the usefulness of every bus cycle.

     //	Randell Jesup			      Lunge Software Development
    //	Dedicated Amiga Programmer            13 Frear Ave, Troy, NY 12180
 \\//	beowulf!lunge!jesup@steinmetz.UUCP    (518) 272-2942
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(-: The Few, The Proud, The Architects of the RPM40 40MIPS CMOS Micro :-)